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DATA SHEET
MOS INTEGRATED CIRCUIT
PD720130
USB2.0 to IDE Bridge
The PD720130 is designed to perform a bridge between USB 2.0 and ATA/ATAPI. The PD720130 complies with the Universal Serial Bus Specification Revision 2.0 full-/high-speed signaling and works up to 480 Mbps. The PD720130 is integrated CISC processor, ATA/ATAPI controller, endpoint controller (EPC), serial interface engine (SIE), and USB2.0 transceiver into a single chip. The USB2.0 protocol and class specific protocol (bulk only protocol) are handled by USB2.0 transceiver, SIE, and EPC. And the transport layer is performed by V30MZ CISC processor which is in the PD720130. The software to control the PD720130 is located in an embedded ROM. In the future, the PD720130 will be released to support external Flash Memory / EEPROMTM option to update function by firmware. Detailed function descriptions are provided in the following user's manual. Be sure to read the manual before designing. PD720130 User's Manual: S16412E
FEATURES
* Compliant with Universal Serial Bus Specification Revision 2.0 (Data Rate 12/480 Mbps) * Compliant with ATA/ATAPI-6 (LBA48, PIO Mode 0-4, Multi Word DMA Mode 0-2, Ultra DMA Mode 0-4) * USB2.0 high-speed bus powered device capability * Certified by USB implementers forum and granted with USB 2.0 high-speed Logo (TID :40320125) * One USB2.0 high-speed transceiver / receiver with full-speed transceiver / receiver * USB2.0 High-speed or Full-speed packet protocol sequencer (Serial Interface Engine) * Automatic chirp assertion and full-/high-speed mode change * USB Reset, Suspend and Resume signaling detection * Supports power control functionality for IDE device as CD-ROM and HDD * Supports set feature (TEST_MODE) functionality * System Clock is generated by 30 MHz X'tal * 2.5 V and 3.3 V power supply
ORDERING INFORMATION
Part Number Package 100-pin plastic TQFP (fine pitch) (14 x 14) 100-pin plastic TQFP (fine pitch) (14 x 14)
PD720130GC-9EU PD720130GC-9EU-SIN
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability and additional information.
Document No. S16302EJ3V0DS00 (3rd edition) Date Published June 2003 NS CP (K) Printed in Japan
The mark
shows major revised points.
2002
PD720130
BLOCK DIAGRAM
CPU Core (V30MZ)
RAM 4 Kbytesx2 ROM
8 Kbytes
EPC2_V2
PHY_V2
USB Bus
DCC
16-bit Bus
Bus Bridge
16-bit Bus
IDEC_V2
IDE Bus
DMAC
GPIO GPIO or FSIO FSIO PIO
INTC
8-bit Bus
Timer
Direct Bus Direct Command Bus
Ext. Bus (Data 8-bit Bus) or PIO
Serial ROM
V30MZ RAM ROM PHY_V2 EPC_V2 IDEC_V2 DCC Bus Bridge INTC GPIO PIO FSIO
: CISC CPU core : 8-Kbyte work RAM for firmware : 8-Kbyte ROM for built-in firmware : USB2.0 transceiver with serial interface engine : Endpoint controller : IDE controller : ATA direct command controller : Internal / external bus controller and DMA controller : Interrupt controller (82C59 like) : General purpose 8-bit I/O controller : Multipurpose 14-bit I/O controller : Flexible serial I/O
2
Data Sheet S16302EJ3V0DS
PD720130
PIN CONFIGURATION (TOP VIEW)
* 100-pin plastic TQFP (fine pitch) (14 x 14)
PD720130GC-9EU PD720130GC-9EU-SIN
VSS SMC VBUS VDD25 AVSS AVDD25 AVSS(R) RREF AVSS AVDD25 VSS RSDM DM VDD33 DP RSDP VSS VDD25 RPU VDD25 TEST2 SCL SDA DPC VSS 100 95 90 85
VDD25 VDD33 XIN XOUT VSS RESETB VDD33 IRQ0 MD0 MD1 IDECS1B IDECS0B IDEA2 IDEA0 IDEA1 VSS IDEINT IDEDAKB IDEIORDY IDEIORB TEST0 TEST1 TEST3 VDD33 VDD25
80
1
75
5
70
10
65
15 60
20 55
30
35
VSS IDEIOWB IDEDRQ IDED15 IDED0 VDD33 IDED14 IDED1 IDED13 IDED2 VDD25 VSS IDED12 IDED3 IDED11 IDED4 IDED10 VDD33 IDED5 IDED9 IDED6 IDED8 IDED7 IDERSTB VSS
40
45
50
25
VDD25 VDD33 CMB_STATE PIO5 CMB_BSY PWR CLC SPD VSS DV0 DV1 DCC PIO14 PIO15 GPIO0 VSS GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 VDD33 VDD25
Data Sheet S16302EJ3V0DS
3
PD720130
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Pin Name VDD25 VDD33 XIN XOUT VSS RESETB VDD33 IRQ0 MD0 MD1 IDECS1B IDECS0B IDEA2 IDEA0 IDEA1 VSS IDEINT IDEDAKB IDEIORDY IDEIORB TEST0 TEST1 TEST3 VDD33 VDD25 Pin No. 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Pin Name VSS IDEIOWB IDEDRQ IDED15 IDED0 VDD33 IDED14 IDED1 IDED13 IDED2 VDD25 VSS IDED12 IDED3 IDED11 IDED4 IDED10 VDD33 IDED5 IDED9 IDED6 IDED8 IDED7 IDERSTB VSS Pin No. 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 Pin Name VDD25 VDD33 GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 VSS GPIO0 PIO15 PIO14 DCC DV1 DV0 VSS SPD CLC PWR CMB_BSY PIO5 CMB_STATE VDD33 VDD25 Pin No. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Pin Name VSS DPC SDA SCL TEST2 VDD25 RPU VDD25 VSS RSDP DP VDD33 DM RSDM VSS AVDD25 AVSS RREF AVSS(R) AVDD25 AVSS VDD25 VBUS SMC VSS
Remark AVSS(R) should be used to connect RREF through 1 % precision reference resistor of 2.43 k.
4
Data Sheet S16302EJ3V0DS
PD720130
1. PIN INFORMATION
(1/2)
Pin Name I/O Buffer Type Active Level Function
XIN XOUT RESETB MD(1:0) IDECS(1:0)B IDEA(2:0) IDEINT IDEDAKB IDEIORDY IDEIORB IDEIOWB IDEDRQ IDED(15:0) IDERSTB DCC DV(1:0) CLC PWR CMB_BSY CMB_STATE DPC SDA SCL VBUS DP DM RSDP RSDM RPU RREF SPD SMC TEST(3:0)
I O I I O (I/O) O (I/O) I (I/O) O (I/O) I (I/O) O (I/O) O (I/O) I (I/O) I/O O (I/O) I (I/O) I (I/O) I (I/O) I (I/O) O (I/O) I (I/O) O (I/O) I/O I/O I I/O I/O O O A A I (I/O) I I
2.5 V Input 2.5 V Output 3.3 V Schmitt Input 3.3 V Input 5 V tolerant Output 5 V tolerant Output 5 V tolerant Input 5 V tolerant Output 5 V tolerant Input 5 V tolerant Output 5 V tolerant Output 5 V tolerant Input 5 V tolerant I/O 5 V tolerant Output 3.3 V Input 3.3 V Input 3.3 V Input 3.3 V Input 3.3 V Output 3.3 V Input 3.3 V Output 3.3 V I/O 3.3 V I/O 5 V Schmitt Input
Note
System clock input or oscillator In Oscillator out Low Asynchronous reset signaling Function mode setting Low IDE host chip select IDE address bus High Low High Low Low High IDE interrupt request from device to host IDE DMA acknowledge IDE IO channel ready IDE IO read strobe IDE IO write strobe IDE DMA request from device to host IDE data bus Low IDE reset from host to device IDE controller operational mode setting Device select System clock setting Bus powered /self-powered select Combo IDE bus busy Combo IDE bus state Power control signaling for IDE device Serial ROM data signaling Serial ROM clock signaling VBUS monitoring USB's high speed D+ signal USB's high speed D- signal USB's full speed D+ signal USB's full speed D- signal USB's 1.5 k pull-up resistor control Reference resistor NEC private Scan mode control Test mode setting
USB high speed D+ I/O USB high speed D- I/O USB full speed D+ Output USB full speed D- Output USB Pull-up control Analog 3.3 V Input 3.3 V Input 3.3 V Input
Note
VBUS pin may be used to monitor for VBUS line even if VDD33, VDD25, and AVDD25 are shut off. System must ensure that the input voltage level for VBUS pin is less than 3.0 V due to the absolute maximum rating is not exceeded.
Data Sheet S16302EJ3V0DS
5
PD720130
(2/2)
Pin Name I/O Buffer Type Active Level Function
GPIO(7:0) PIO(15:14) PIO(5) IRQ0 AVDD25 VDD25 VDD33 AVSS VSS
I/O I/O I/O I
3.3 V Schmitt I/O 3.3 V I/O 3.3 V Schmitt I/O 3.3 V Schmitt Input High
General purpose IO port (for future extension) IO port (for future extension) IO port (for future extension) External interrupt input (for future extension) 2.5 V VDD for Analog circuit 2.5 V VDD 3.3 V VDD VSS for Analog circuit VSS
Remarks 1. "5 V tolerant" means that the buffer is 3.3 V buffer with 5 V tolerant circuit. 2. The signal marked as "(I/O)" in the above table operates as I/O signals during testing. However, they do not need to be considered in normal use.
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Data Sheet S16302EJ3V0DS
PD720130
2. FUNCTION INFORMATION
USB to IDE system can be realized by the PD720130, Serial ROM which has USB vender ID, product ID, etc, and power control circuit. The PD720130 can be selected bus powered mode or self powered mode. If all power consumption for USB to IDE system is less than the specification of bus powered device, it will be possible to realize high-speed capable bus powered system. The PD720130 has some features for bus powered system. Also, some system may control target IDE device by two IDE controllers. At the time, IDE bus arbitration should be required to each IDE controller. The PD720130 has a feature of IDE bus arbitration, too. The setting of IDE controller in the PD720130 is controlled by data in serial ROM or external pin setting. If there is any inconsistency between data in serial ROM and external pin setting, the data in serial ROM is higher priority than external pin setting. 2.1 Data in Serial ROM The PD720130 loads some data such as Vendor ID, Product ID and some additional USB related information, etc from serial ROM when the PD720130 is initialized. Example of data in serial ROM is as follows. ExPinReset and ExPinSet fields hold data which is related to the external pin setting. Table 2-1. Data in Serial ROM
Data size 1 Word 1 Byte 1 Byte 1 Word 1 Word 1 Word 1 Byte 1 Byte 1 Byte 1 Byte 1 Byte 1 Word 1 Word 32 Bytes 32 Bytes 32 Bytes Flags ExPinReset ExPinSet idVendor idProduct bcdDevice MaxPower BUS MaxPower Self bInterfaceClass bInterfaceSubClass bInterfaceProtocol TxMode Reset TxMode Set ManufactureString ProductString SerialString Symbol Description Control for descriptor overwrite PWR, CLC, DCC, DV[1:0] Reset bit map field PWR, CLC, DCC, DV[1:0] Set bit map field idVendor field in Device descriptor idProduct field in Device descriptor bcdDevice field in Device descriptor MaxPower field in Configuration descriptor for Bus powered mode MaxPower field in Configuration descriptor for Self powered mode bInterfaceClass field in Interface descriptor bInterfaceSubClass field in Interface descriptor bInterfaceProtocol field in Interface descriptor IDE transmission type such as Ultra DMA 66 Reset bit map field IDE transmission type such as Ultra DMA 66 Set bit map field String descriptor for Manufacturer String descriptor for Product String descriptor for Device serial number
Data Sheet S16302EJ3V0DS
7
PD720130
2.2 External Pin Setting Usually, serial ROM should be used to keep Vendor ID, Product ID and some additional USB related information. And then, the external pin setting of the PD720130 is not so important to realize USB to IDE bridge system. The recommended external pin setting is as follows. Table 2-2. Recommended External Pin Setting
Pin Name MD1 MD0 SCL SDA DV1 DV0 CLC PWR DCC GPIO(7:0) PIO(14:15) PIO5 SPD TEST(3:0) SMC IRQ0 1 0 Pull Up Note 1 Pull Up "L" clamp "L" clamp "L" clamp "L" clamp Pull Down Note 2 "L" clamp "L" clamp "L" clamp "H" clamp "L" clamp "L" clamp "L" clamp Setting
Notes 1. 2.
If serial ROM size is more than 2 Kbytes, SCL should be pull down. If target IDE device is not fixed, it is preferable that DCC pin can switch pull-up or pull-down.
The setting for any other pins such as CMB_BSY, CMB_STATE depends on USB2.0 to IDE Bridge system. For example, if two IDE controllers control one target IDE device and one of two IDE controllers is the PD720130, CMB_BSY and CMB_STATE are used to handshake between two IDE controller chips. On the other hand, when the PD720130 is only controller of target IDE device, CMB_BSY should be opened and CMB_STATE should be clamped to "L".
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Data Sheet S16302EJ3V0DS
PD720130
2.3 Control Bit in Serial ROM or External Pin Setting The following tables show IDE status and control bit in serial ROM or external pin setting. Table 2-3. DV1/DV0, CLC, PWR Setting
No. Device Power Internal Clock 7.5 MHz ATA/ATAPI Setting in Serial ROM or External Pin PWR No device connected ATA ATAPI Reserved 60 MHz No device connected ATA ATAPI Reserved Self Powered 60 MHz No device connected Combo (ATA) Combo (ATAPI) Reserved No device connected ATA ATAPI Auto device detect 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 CLC 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 DV1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 DV0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Bus Powered
Remark
Setting No. 0, 3, 4, 7, 8, 11, and 12 are prohibited to use.
Data Sheet S16302EJ3V0DS
9
PD720130
Table 2-4. DV1/DV0, DCC Setting
Condition DV1 DV0 Mode Target Device ATA DCC Pin Setting 0 0 0 1 1 1 0 1 ATAPI ATAPI 0 0 0 1 1 1 0 0 Auto device detect ATA 0 0 0 1 1 1 ATAPI 0 0 0 1 1 1 DCC Setting in Serial ROM No setting Reset Set No setting Reset Set No setting Reset Set No setting Reset Set No setting Reset Set No setting Reset Set No setting Reset Set No setting Reset Set Description
1
0
ATA
Ultra, Multi Word DMA are disabled Ultra, Multi Word DMA are disabled Ultra, Multi Word DMA are enabled. Ultra, Multi Word DMA are enabled. Ultra, Multi Word DMA are disabled Ultra, Multi Word DMA are enabled. Ultra DMA is disabled Ultra DMA is disabled Ultra, Multi Word DMA are enabled. Ultra, Multi Word DMA are enabled. Ultra DMA is disabled Ultra, Multi Word DMA are enabled. Ultra, Multi Word DMA are disabled Ultra, Multi Word DMA are disabled Ultra, Multi Word DMA are enabled. Ultra, Multi Word DMA are enabled. Ultra, Multi Word DMA are disabled Ultra, Multi Word DMA are enabled. Ultra DMA is disabled Ultra DMA is disabled Ultra, Multi Word DMA are enabled. Ultra, Multi Word DMA are enabled. Ultra DMA is disabled Ultra, Multi Word DMA are enabled.
Remark
PIO mode 0-4 are always enabled.
10
Data Sheet S16302EJ3V0DS
PD720130
2.4 Combo Mode Function The PD720130 can be used to realize that two IDE controller chips control one target IDE device in one system. To realize IDE bus arbitration between two IDE controller chips, the PD720130 has CMB_BSY and CMB_STATE. Combo mode is enabled when PWR = 0 and CLC = 1. CMB_BSY and CMB_STATE connect to other IDE controller chip as follows. Figure 2-1. CMB_BSY and CMB_STATE Connection between Two IDE Controller Chips
PD720130
Other IDE controller
CMB_STATE CMB_BSY
IDE Bus Grant IDE Bus Request
Table 2-5. Description of CMB_BSY and CMB_STATE
Pin Name CMB_STATE Direction IN Value 0 1 CMB_BSY OUT 0 1 Description Other IDE controller does not require or does not use IDE bus. Other IDE controller requires or is using IDE bus. The PD720130 does not require or does not use IDE bus. The PD720130 requires or is using IDE bus.
Data Sheet S16302EJ3V0DS
11
PD720130
The IDE bus arbitration will be done by following sequence. The PD720130 will confirm whether other IDE controller requires or is using IDE bus or not. If other IDE controller does not require or does not use IDE bus, the PD720130 will use IDE bus. Figure 2-2. IDE Bus Arbitration Sequence
START
Chip Init
CMB_STATE = 1? Yes. No.
Other IDE controller requires or is using IDE bus.
CMB_BSY = 1
CMB_STATE = 0? Yes. No. The PD720130 can not use IDE bus
CMB_BSY = 0
IDE bus is used by the PD720130
END
12
Data Sheet S16302EJ3V0DS
PD720130
2.5 Power Control To realize bus-powered or high performance self-powered USB2.0 to IDE Bridge system, the PD720130 has two internal system clock mode. One is 7.5 MHz for bus-powered mode and the other is 60 MHz for self-powered mode. The PD720130 controls the power state by events as follows. The word with under line shows event. The Italic word shows the power state. Figure 2-3. Power State Control (a) Bus-powered Mode
Power OFF Power OFF Vbus OFF
Vbus ON Connect Hardware Reset Idle Mode
Power = PRESET
Bus Reset FS CONNECT
Default State
HS CONNECT
FS Enumeration State
Power = PENUM_FS
Resume Suspend Resume
HS Enumeration State
Set Configuration
Suspend
Power = PENUM_HS
Resume
Set Configuration
Suspend Mode
Suspend Suspend Resume Resume
Suspend Mode
Configured State
Configured State
Suspend
FS Operation State
Power = PSPND
Suspend
HS Operation State
Power = PSPND
Resume
Power = PFS_B
Power = PHS_B
(b) Self-powered Mode
Power OFF
Power OFF
Power ON Hardware Reset Idle Mode Power = PRESET CMB_STATE = 0 CMB_STATE = 1 Bus Reset
IDE Bus Release State
Disconnect Mode
Vbus OFF
Vbus ON Connect
Default State
FS CONNECT
HS CONNECT
Power = PCOMBO
FS Enumeration
State
Resume
HS Enumeration State
Power = PENUM_FS
Set Configuration
Suspend Suspend Resume Suspend
Power = PENUM_HS Set Configuration
Suspend Mode Configured State
Resume Suspend Resume
Suspend
Suspend Mode
Configured State
Power = PSPND
Suspend
HS Operation State
Power = PSPND
Resume
FS Operation State
Resume
Power = PFS_S
Power = PHS_S
Data Sheet S16302EJ3V0DS
13
PD720130
To realize bus-powered USB2.0 to IDE Bridge system, the power consumption for IDE device should be controlled by the power state of the PD720130. The PD720130 has DPC pin to control IDE device's power circuit. DPC pin's output level relates to USB device states. DPC should be pull up to 3.3 V because DPC output becomes high impedance state until the PD720130 is initialized. Figure 2-4. DPC Pin to Control IDE Device's Power Circuit
High impedance state
Default
Un-configured
Configured
Suspend
Configured
DPC
Normal Operation
Normal Operation
Power ON Hardware Reset
Bus Reset
Set Configuration
Suspend Occured
Resume Occured
Following reference circuit can cut off power supply to IDE device during the PD720130 is under default and un-configured state. Also, the power supply to IDE device is disabled during suspend state, too. Power consumption of total system under default, un-configured, and suspend state can be reduced by DPC pin. Figure 2-5. Power Control Circuit Example
Power supply rail IDE Device 3.3 V Pull Up IN OUT Regulator Power
PD720130
P-Channel Switch
DPC
ON
14
Data Sheet S16302EJ3V0DS
PD720130
3.
3.1 * * * * * * * * * * *
ELECTRICAL SPECIFICATIONS
Buffer List 2.5 V oscillator interface XIN, XOUT 3.3 V input buffer MD(1:0), TEST(3:0), SMC 3.3 V schmitt input buffer RESETB, IRQ0 3.3 V input buffer with enable (OR type) DCC, DV(1:0), SPD, CLC, PWR, CMB_STATE 3.3 V IOL = 6 mA 3-state output buffer CMB_BSY, DPC 3.3 V IOL = 3 mA bi-directional schmitt buffer with input enable (OR-type) GPIO(7:0), PIO5, SDA, SCL 3.3 V IOL = 6 mA bi-directional buffer with input enable (OR-type) PIO(15:14) 5 V schmitt input buffer VBUS 5 V IOL = 6 mA 3-state output buffer IDECS(1:0)B, IDEA(2:0), IDEDAKB, IDEIORB, IDEIOWB, IDERSTB 5 V IOL = 6 mA bi-directional buffer with input enable (OR-type) IDED(15:0), IDEINT, IDEIORDY, IDEDRQ USB interface DP, DM, RSDP, RSDM, RREF, RPU Remark Above, "5 V" refers to a 3.3 V buffer with 5-V tolerant circuit. Therefore, it is possible to have a 5-V connection for an external bus, but the output level will be only up to 3.3 V, which is the VDD33 voltage.
Data Sheet S16302EJ3V0DS
15
PD720130
3.2 Terminology
Terms Used in Absolute Maximum Ratings
Parameter Power supply voltage Symbol Meaning
VDD33, VDD25 Indicates voltage range within which damage or reduced reliability will not result when power is applied to a VDD pin. VI Indicates voltage range within which damage or reduced reliability will not result when power is applied to an input pin. Indicates voltage range within which damage or reduced reliability will not result when power is applied to an output pin. Indicates absolute tolerance value for DC current to prevent damage or reduced reliability when a current flows out of or into an output pin. Indicates the ambient temperature range for normal logic operations. Indicates the element temperature range within which damage or reduced reliability will not result while no voltage or current are applied to the device.
Input voltage
Output voltage
VO
Output current
IO
Operating temperature Storage temperature
TA Tstg
Terms Used in Recommended Operating Range
Parameter Power supply voltage High-level input voltage Symbol Meaning
VDD33, VDD25 Indicates the voltage range for normal logic operations occur when VSS = 0 V. VIH Indicates the voltage, which is applied to the input pins of the device, is the voltage indicates that the high level states for normal operation of the input buffer. * If a voltage that is equal to or greater than the "Min." value is applied, the input voltage is guaranteed as high level voltage.
Low-level input voltage
VIL
Indicates the voltage, which is applied to the input pins of the device, is the voltage indicates that the low level states for normal operation of the input buffer. * If a voltage that is equal to or lesser than the "Max." value is applied, the input voltage is guaranteed as low level voltage.
Hysteresys voltage
VH
Indicates the differential between the positive trigger voltage and the negative trigger voltage. Indicates allowable input rise time to input pins. Input rise time is transition time from 0.1 x VDD to 0.9 x VDD. Indicates allowable input fall time to input pins. Input fall time is transition time from 0.9 x VDD to 0.1 x VDD.
Input rise time
tri
Input fall time
tfi
Terms Used in DC Characteristics
Parameter Off-state output leakage current Output short circuit current Symbol IOZ Meaning Indicates the current that flows from the power supply pins when the rated power supply voltage is applied when a 3-state output has high impedance. Indicates the current that flows when the output pin is shorted (to GND pins) when output is at high-level. Indicates the current that flows when the input voltage is supplied to the input pin. Indicates the current that flows to the output pins when the rated low-level output voltage is being applied. Indicates the current that flows from the output pins when the rated high-level output voltage is being applied.
IOS
Input leakage current Low-level output current
II IOL
High-level output current
IOH
16
Data Sheet S16302EJ3V0DS
PD720130
3.3 Electrical Specifications
Absolute Maximum Ratings
Parameter Power supply voltage Symbol VDD33 VDD25 Input voltage, 5 V buffer VI Condition 3.3 V power supply rail 2.5 V power supply rail 3.0 V VDD33 3.6 V VI < VDD33 + 3.0 V 3.0 V VDD33 3.6 V VI < VDD33 + 1.0 V 2.3 V VDD25 2.7 V VI < VDD25 + 0.9 V 3.0 V VDD33 3.6 V VO < VDD33 + 3.0 V 3.0 V VDD33 3.6 V VO < VDD33 + 1.0 V 2.3 V VDD25 2.7 V VO < VDD25 + 0.9 V IOL = 6 mA IOL = 6 mA IOL = 3 mA Operating ambient temperature Storage temperature TA Tstg Rating -0.5 to +4.6 -0.5 to +3.6 -0.5 to +6.6 -0.5 to +4.6 -0.5 to +3.6 -0.5 to +6.6 -0.5 to +4.6 -0.5 to +3.6 Unit V V V
Input voltage, 3.3 V buffer
VI
V
Input voltage, 2.5 V buffer
VI
V
Output voltage, 5 V buffer
VO
V
Output voltage, 3.3 V buffer
VO
V
Output voltage, 2.5 V buffer
VO
V
Output current, 5 V buffer Output current, 3.3 V buffer
IO IO
20 20 10 0 to +70 -65 to +150
mA mA mA C C
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameters. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. The ratings and conditions indicated for DC characteristics and AC characteristics represent the quality assurance range during normal operation. Two Power Supply Rails Limitation The PD720130 has two power supply rails (2.5 V, 3.3 V). The system will require the time when power supply rail is stable at VDD level. And, there will be difference between the time of VDD25 and VDD33. The PD720130 requires that VDD25 should be stable before VDD33 becomes stable. At this case, the system must ensure that the absolute maximum ratings for VI / VO are not exceeded. System reset signaling should be asserted more than specified time after both VDD25 and VDD33 are stable.
Data Sheet S16302EJ3V0DS
17
PD720130
Recommended Operating Ranges
Parameter Operating voltage Symbol VDD33 VDD25 VDD25 High-level input voltage 5.0 V high-level input voltage 3.3 V high-level input voltage 2.5 V high-level input voltage Low-level input voltage 5.0 V low-level input voltage 3.3 V low-level input voltage 2.5 V low-level input voltage Hysteresis voltage 5 V hysteresis voltage 3.3 V hysteresis voltage Input rise time Normal buffer Schmitt buffer Input fall time Normal buffer Schmitt buffer tfi 0 0 200 10 ns ms tri 0 0 200 10 ns ms VH 0.3 0.2 1.5 1.0 V V VIL 0 0 0 0.8 0.8 0.7 V V V VIH 2.0 2.0 1.7 5.5 VDD33 VDD25 V V V Condition 3.3 V for VDD33 pins 2.5 V for VDD25 pins 2.5 V for AVDD25 pins Min. 3.0 2.3 2.3 Typ. 3.3 2.5 2.5 Max. 3.6 2.7 2.7 Unit V V V
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Data Sheet S16302EJ3V0DS
PD720130
DC Characteristics (VDD33 = 3.0 to 3.6 V, VDD25 = 2.3 to 2.7 V, TA = 0 to +70C) Control Pin Block
Parameter Off-state output current Output short circuit current Low-level output current 5.0 V low-level output current 3.3 V low-level output current 3.3 V low-level output current High-level output current 5.0 V high-level output current 3.3 V high-level output current 3.3 V high-level output current Input leakage current 3.3 V buffer 5.0 V buffer II VI = VDD or VSS VI = VDD or VSS 10 10 IOH VOH = 2.4 V VOH = 2.4 V VOH = 2.4 V -2.0 -6.0 -3.0 mA mA mA Symbol IOZ IOS Note IOL VOL = 0.4 V VOL = 0.4 V VOL = 0.4 V 6.0 6.0 3.0 mA mA mA Condition VO = VDD33, VDD25 or VSS Min. Max. 10 -250 Unit
A
mA
A A
Note The output short circuit time is one second or less and is only for one pin on the LSI.
Data Sheet S16302EJ3V0DS
19
PD720130
USB Interface Block
Parameter Serial Resistor between DP (DM) and RSDP (RSDM) Output pin impedance Bus pull-up resistor on upstream facing port Symbol RS Conditions Min. 38.61 Max. 39.39 Unit
ZHSDRV RPU
Includes RS resistor 1.5 k 5% consists of resistance of transistor and pull-up resistor
40.5 1.485
49.5 1.515
Termination voltage for upstream facing port pull-up Input Levels for Full-speed: High-level input voltage (drive) High-level input voltage (floating) Low-level input voltage Differential input sensitivity Differential common mode range Output Levels for Full-speed: High-level output voltage Low-level output voltage SE1 Output signal crossover point voltage Input Levels for High-speed: High-speed squelch detection threshold (differential signal) High-speed disconnect detection threshold (differential signal) High-speed data signaling common mode voltage range High-speed differential input signaling level Output Levels for High-speed: High-speed idle state High-speed data signaling high High-speed data signaling low Chirp J level (differential signal) Chirp K level (differential signal)
VTERM
3.0
3.6
V
VIH VIHZ VIL VDI VCM (D+) - (D-) Includes VDI range
2.0 2.7 3.6 0.8 0.2 0.8 2.5
V
V V V
VOH VOL VOSE1 VCRS
RL of 14.25 k to VSS RL of 1.425 k to 3.6 V
2.8 0.0 0.8 1.3
3.6 0.3
V V V
2.0
V
VHSSQ
100
150
mV
VHSDSC
525 -50
625 +500
mV
VHSCM
mV
See Figure 3-4.
VHSOI VHSOH VHSOL VCHIRPJ VCHIRPK
-10.0 360 -10.0 700 -900
+10.0 440 +10.0 1100 -500
mV mV mV mV mV
20
Data Sheet S16302EJ3V0DS
PD720130
Figure 3-1. Differential Input Sensitivity Range for Low-/full-speed
Differential Input Voltage Range Differential Output Crossover Voltage Range
-1.0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 4.6
Input Voltage Range (V)
Figure 3-2. Full-speed Buffer VOH/IOH Characteristics for High-speed Capable Transceiver
VDD-3.3
VDD-2.8 VDD-2.3
VDD-1.8 VDD-1.3 VDD-0.8
VDD-0.3 VDD 0
-20
IOUT (mA)
-40 Min. -60 Max. -80 VOUT (V)
Figure 3-3. Full-speed Buffer VOL/IOL Characteristics for High-speed Capable Transceiver
80 Max. 60 Min. 40
IOUT (mA)
20
0 0 0.5 1 1.5 VOUT (V) 2 2.5 3
Data Sheet S16302EJ3V0DS
21
PD720130
Figure 3-4. Receiver Sensitivity for Transceiver at DP/DM
Level 1
+400 mV Differential
Point 3
Point 4
Point 1
Point 2
0V Differential
Point 5
Point 6
Level 2
-400 mV Differential
0%
Unit Interval
100%
Figure 3-5. Receiver Measurement Fixtures
Test Supply Voltage 15.8 USB Connector Nearest Device Vbus D+ DGnd 50 Coax 50 Coax + To 50 Inputs of a High Speed Differential Oscilloscope, or 50 Outputs of a High Speed Differential Data Generator -
15.8
143
143
Pin Capacitance
Parameter Input capacitance Output capacitance I/O capacitance Symbol CIN COUT CIO Condition VDD = 0 V, TA = 25C fC = 1 MHz Unmeasured pins returned to 0 V Min. 4 4 4 Max. 6 6 6 Unit pF pF pF
22
Data Sheet S16302EJ3V0DS
PD720130
Power Consumption (1) The power consumption when device works as bus-powered mode
Symbol Condition VDD25 PENUM-BUS The power consumption under unconfigured stage High-speed operating Full-speed operating PW-BUS The power consumption when device works High-speed operating Full-speed operating PW_SPD-BUS The power consumption under suspend state 110 113 10 22 13 235 10 10 5 mA mA 57 23 3 4 10 10 mA mA Max. VDD33 AVDD25 Unit
A
(2) The power consumption when device works as self-powered mode
Symbol Condition VDD25 PENUM-SELF The power consumption under unconfigured stage High-speed operating Full-speed operating PW-SELF The power consumption when device works High-speed operating Full-speed operating PW_SPD-SELF PW_UNP PW_COM The power consumption under suspend state The power consumption under unplug state The power consumption under combo mode The device is releasing the IDE bus. 120 113 50 87 90 25 13 5 3 5 10 10 5 10 10 mA mA mA mA mA 85 60 5 5 10 10 mA mA Max. VDD33 AVDD25 Unit
Data Sheet S16302EJ3V0DS
23
PD720130
AC Characteristics (VDD33 = 3.0 to 3.6 V, VDD25 = 2.3 to 2.7 V, TA = 0 to +70C) System Clock Ratings
Parameter Clock frequency Symbol fCLK X'tal Condition Min. -500 ppm Oscillator block -500 ppm Clock duty cycle tDUTY 45 50 30 Typ. 30 Max. +500 ppm +500 ppm 55 % MHz Unit MHz
Remarks 1. Recommended accuracy of clock frequency is 100 ppm. 2. Required accuracy of X'tal or Oscillator block is including initial frequency accuracy, the spread of X'tal capacitor loading, supply voltage, temperature, and aging, etc. System Reset signaling
Parameter Reset active time Symbol trst Conditions Min. 2 Max. Unit
s
USB Interface Block (1/2)
Parameter Full-speed Source Electrical Characteristics Rise time (10% - 90%) tFR CL = 50 pF, RS = 36 CL = 50 pF, RS = 36 (tFR/tFF) Average bit rate 4 20 ns Symbol Conditions Min. Max. Unit
Fall time (90% - 10%)
tFF
4
20
ns
Differential rise and fall time matching Full-speed data rate for device which are high-speed capable Frame interval Consecutive frame interval jitter Source jitter total (including frequency tolerance): To next transition For paired transitions Source jitter for differential transition to SE0 transition Receiver jitter: To next transition For paired transitions Source SE0 interval of EOP Receiver SE0 interval of EOP Width of SE0 interval during differential transition
tFRFM tFDRATHS
90 11.9940
111.11 12.0060
% Mbps
tFRAME tRFI No clock adjustment
0.9995
1.0005 42
ms ns
tDJ1 tDJ2 tFDEOP
-3.5 -4.0 -2
+3.5 +4.0 +5
ns ns ns
tJR1 tJR2 tFEOPT tFEOPR tFST
-18.5 -9 160 82
+18.5 +9 175
ns ns ns ns
14
ns
24
Data Sheet S16302EJ3V0DS
PD720130
(2/2)
Parameter Symbol Conditions Min. Max. Unit
High-speed Source Electrical Characteristics Rise time (10% - 90%) Fall time (90% - 10%) Driver waveform High-speed data rate Microframe interval Consecutive microframe interval difference tHSR tHSF See Figure 3-6. tHSDRAT tHSFRAM tHSRFI 479.760 124.9375 480.240 125.0625 4 highspeed Mbps 500 500 ps ps
s
Bit times
Data source jitter Receiver jitter tolerance Device Event Timings Time from internal power good to device pulling D+ beyond VIHZ (min.) (signaling attached) Debounce interval provided by USB system software after attach Inter-packet delay for full-speed
See Figure 3-6. See Figure 3-4.
tSIGATT
100
ms
tATTDB
100
ms
Bit times
tIPD
2
Inter-packet delay for device response w/detachable cable for full-speed High-speed detection start time from suspend Sample time for suspend vs reset Time to detect bus suspend state Power down under suspend Reversion time from suspend to highspeed Drive Chirp K width Finish Chirp K assertion Start sequencing Chirp K-J-K-J-K-J Finish sequencing Chirp K-J Detect sequencing Chirp K-J width Sample time for sequencing Chirp Reversion time to high-speed High-speed detection start time Reset completed time
tRSPIPD1
6.5
Bit times
tSCA
2.5
s s
ms ms
tCSR tSPD tSUS tRHS
100 3.000
875 3.125 10 1.333
s
ms
tCKO tFCA tSSC tFSC tCSI tSCS tRHA tHDS tDRS
1 7 100 -500 2.5 1 2.5 500 2.5 10 3000 -100
ms
s s s
ms
s s
ms
Data Sheet S16302EJ3V0DS
25
PD720130
IDE Interface Block PIO mode
Parameter Cycle time (min.) Address setup time (min.) 16 bits DIOR/DIOW pulse width (min.) 8 bits DIOR/DIOW pulse width (min.) DIOR/DIOW recovery time (min.) DIOW data setup time (min.) DIOW data hold time (min.) DIOR data setup time (min.) DIOR data hold time (min.) DIOR 3-state delay time (max.) Address hold time (min.) IORDY read data valid time (min.) IORDY setup time (min.)
Note Note
Symbol t0 t1 t2
Mode 0 600 70 165 290
Mode 1 383 50 125 290 - 45 20 35 5 30 15 0 35 1250 5
Mode 2 240 30 100 290 - 30 15 20 5 30 10 0 35 1250 5
Mode 3 180 30 80 80 70 30 10 20 5 30 10 0 35 1250 5
Mode 4 120 25 70 70 25 20 10 20 5 30 10 0 35 1250 5
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
t2i t3 t4 t5 t6 t6Z t9 tRD tA tB
Note
- 60 30 50 5 30 20 0 35 1250 5
IORDY pulse width (max.)
Note
IORDY Inactive to Hi-Z time (max.)
tC
Note IORDY is an option in mode 0 - 2. IORDY is essential in modes 3 and 4. Multi Word DMA mode
Parameter Cycle time (min.) DIOR/DIOW pulse width (min.) DIOR data access time (max.) DIOR data hold time (min.) DIOR data setup time (min.) DIOW data setup time (min.) DIOW data hold time (min.) DMACK setup time (min.) DMACK hold time (min.) DIOR negate pulse width (min.) DIOW negate pulse width (min.) DIOR-DMARQ delay time (max.) DIOW-DMARQ delay time (max.) DMACK 3-state delay time (max.) CS setup time (min.) CS hold time (min.) Symbol t0 tD tE tF tGr tGw tH tI tJ tKr tKw tLr tLw tZ tM tN Mode 0 480 215 150 5 100 100 20 0 20 50 215 120 40 20 50 15 Mode 1 150 80 60 5 30 30 15 0 5 50 50 40 40 25 30 10 Mode 2 120 70 50 5 20 20 10 0 5 25 25 35 35 25 25 10 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
26
Data Sheet S16302EJ3V0DS
PD720130
Ultra DMA mode
Parameter Symbol Mode 0 Min. Average cycle time for 2 cycles Minimum cycle time for 2 cycles Cycle time for 1 cycle Data setup time on receive side Data hold time on receive side Data setup time on transmit side Data hold time on transmit side First STROBE time Interlock time with limitation Minimum interlock time Interlock time without limitation Output release time Output delay time Output stabilization time (from release) Envelope time STROBE DMARDY delay time Last STROBE time Pause time IORDY pull-up time IORDY wait time DMACK setup/hold time STROBE STOP time t2CYC t2CYC tCYC tDS tDH tDVS tDVH tFS tLI tMLI tUI tAZ tZAH tZAD 240 235 114 15 5 70 6 0 0 20 0 20 0 Max. 230 150 10 Mode 1 Min. 160 156 75 10 5 48 6 0 0 20 0 20 0 Max. 200 150 10 Mode 2 Min. 120 117 55 7 5 34 6 0 0 20 0 20 0 Max. 170 150 10 Mode 3 Min. 90 86 39 7 5 20 6 0 0 20 0 20 0 Max. 130 100 10 Mode 4 Min. 60 57 25 5 5 6 6 0 0 20 0 20 0 Max. 120 100 10 ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
tENV tSR tRFS tRP tIORYZ tZIORY tACK tSS
20 160 0 20 50
70 50 75 20 -
20 125 0 20 50
70 30 60 20 -
20 100 0 20 50
70 20 50 20 -
20 100 0 20 50
55 NA 60 20 -
20 100 0 20 50
55 NA 60 20 -
ns ns ns ns ns ns ns ns
Data Sheet S16302EJ3V0DS
27
PD720130
Serial ROM interface Block
Parameter Clock frequency Clock pulse width low Clock pulse width high Clock Low to data valid Start hold time Start setup time Data in hold time Data in setup time Data out hold time Stop setup time Time the bus must be free before a new transmission can start Write cycle time Symbol tSCL tLOW tHIGH tAA tHD.STA tSU.STA tHD.DAT tSU.DAT tDH tSU.STO tBUF 4.7 4.0 100 4.0 4.7 0 0.2 50 4.7 10 4500 Conditions Min. Max. 100 Unit KHz
s s
ns
s s
ns
s
ns
s s
ms
tWR
10
28
Data Sheet S16302EJ3V0DS
PD720130
Figure 3-6. Transmit Waveform for Transceiver at DP/DM
Level 1
Point 3 Point 4
+400 mV Differential
Point 1
Point 2
0V Differential
Point 5
Point 6
Level 2 Unit Interval 0% 100%
-400 mV Differential
Figure 3-7. Transmitter Measurement Fixtures
Test Supply Voltage 15.8 USB Connector Nearest Device Vbus D+ DGnd 50 Coax 50 Coax + To 50 Inputs of a High Speed Differential Oscilloscope, or 50 Outputs of a High Speed Differential Data Generator -
15.8
143
143
Data Sheet S16302EJ3V0DS
29
PD720130
Timing Diagram System reset timing
trst RESETB
Remark After RESET is negated, this chip read the serial ROM first. Do not reset while the serial ROM is read. The serial ROM is completed to read below time, after RESET is negated. 5 + 0.1197 x bytes (serial ROM size) + 0.5678 (ms) Example In the case of 512 bytes: 66.855 ms, in the case of 8 Kbytes: 986.15 ms USB power-on and connection events
Hub port power OK Hub port power-on VBUS VIH(min) VIH D+ or D-
Attatch detected
Reset recovery time
4.01 V
USB system software reads device speed
tSIGATT tATTDB
10 ms
USB differential data jitter for full-speed
tPERIOD Differential Data Lines Crossover Points
Consecutive Transitions N x tPERIOD + tDJ1 Paired Transitions N x tPERIOD + tDJ2
30
Data Sheet S16302EJ3V0DS
PD720130
USB differential-to-EOP transition skew and EOP width for full-speed
tPERIOD Differential Data Lines Crossover Point Crossover Point Extended
Diff. Data-toSE0 Skew N x tPERIOD + tFDEOP
Source EOP Width: tFEOPT Receiver EOP Width: tFEOPR
USB receiver jitter tolerance for full-speed
tPERIOD Differential Data Lines
tJR
tJR1
tJR2
Consecutive Transitions N x tPERIOD + tJR1 Paired Transitions N x tPERIOD + tJR2
USB connection sequence on full-speed system bus
Pull-up is active. USB bus FSJ tHDS tFCA tDRS T0 tSCA tCKO tSCS Chirp K device out Reversion to full-speed mode FSJ
USB connection sequence on high-speed system bus
Pull-up is active. Chirp K device out USB bus FSJ tHDS tFCA T0
tSCA
Chirp state from host/hub K J K J K J K
Reversion to high-speed mode J tRHA Reset Complete
tCKO
tSSC tCSI tSCS
tFSC
Data Sheet S16302EJ3V0DS
31
PD720130
USB reset sequence from suspend state on full-speed system bus
Pull-up is active. USB bus FSJ tSCA tFCA tDRS T0 tCKO tSCS Chirp K device out FSJ
USB reset sequence from suspend state on high-speed system bus
Pull-up is active. USB bus FSJ tSCA tFCA T0 tCKO Chirp K device out K tSSC tCSI Chrip state from host/hub J K J K J K J tRHA tSCS tFSC Reversion to high-speed mode Reset Complete
USB suspend and resume on full-speed system bus
FS EOP USB bus tSPD tSUS
Power will be down
FSJ
FSK
FSJ
Note time required to relock PLL and stabilize oscillator.
USB suspend and resume on high-speed system bus
Reversion to full-speed mode High-speed packet USB bus tSPD T0 t tCSR tSUS FSJ FSK tRHS
Power will be down
Reversion to high-speed mode High-speed packet
Note time required to relock PLL and stabilize oscillator.
32
Data Sheet S16302EJ3V0DS
PD720130
IDE PIO mode timing
IDECS1B, IDECS0B IDEEA2-IDEEA0 IDEIORB IDEIOWB IDED15-IDED0 (WRITE) IDED15-IDED0 (READ)
H L H L H L
t1
t0 t2 t3
t9 t2i t4
t5 H L tA IDEIORDY H L tB tRD tC
t6Z t6
IDE multi word DMA mode timing
IDECS1B, IDECS0B IDEDRQ IDEDAKB IDEIORB IDEIOWB IDED15-IDED0 (READ) IDED15-IDED0 (WRITE) H L H L H L tI H L H L H L tE tD tGr tGw tF tH tKr/tKw tM tLr/tLw t0 tJ tZ
tN
IDE ultra DMA mode data-in timing
IDEDRQ IDEDAKB IDEIOWB (STOP) IDEIORDY (HDMARDY) IDEIORB (DSTROBE) IDED15-IDED0 IDECS1B, IDECS0B IDEA2-IDEA0 H L H L H L H L H L H L H L H L tAZ tACK tACK tUI tACK tACK tENV tENV tZIORY tDVS
Data
tSS tFS tZAD tFS tZAD t2CYC tCYC tDVH
Data
tLI
tLI tLI
tMLI
tACK tACK tIORYZ
tCYC
Data
tZAH tDVS tAZ
CRC
tDVH tACK tACK
Data Sheet S16302EJ3V0DS
33
PD720130
IDE ultra DMA mode data-in stop timing
IDEDRQ IDEDAKB IDEIOWB (STOP) IDEIORB (HDMARDY) IDEIORDY (DSTROBE) IDED15-IDED0 H L H L tRP H L H L H L H L tSR tRFS
IDE ultra DMA mode data-in end timing
IDEDRQ IDEDAKB IDEIOWB (STOP) IDEIORB (HDMARDY) IDEIORDY (DSTROBE) IDED15-IDED0 IDECS1B, IDECS0B IDEA2-IDEA0 H L H L
tLI
tMLI
tACK
H L
tZAH tRP tAZ tLI tMLI tACK tIORYZ tDVS tDVH
CRC
H L H L H L H L
tRPS
tACK
IDE ultra DMA mode data-out timing
IDEDRQ IDEDAKB IDEIOWB (STOP) IDEIORDY (DDMARDY) IDEIORB (HSTROBE) IDED15-IDED0 IDECS1B, IDECS0B IDEA2-IDEA0 H L H L H L H L H L H L H L H L tZIORY tACK tDVS
Data
tUI tACK tENV tLI tUI tRFS t2CYC tCYC tDVH
Data
tRP tMLI tACK tIORYZ tLI tCYC
Data
tLI
tMLI tDVS
CRC
tACK tDVH tACK tACK
tACK tACK
34
Data Sheet S16302EJ3V0DS
PD720130
IDE ultra DMA mode data-out stop timing
IDEDRQ IDEDAKB IDEIOWB (STOP) IDEIORB (HDMARDY) IDEIORDY (DSTROBE) IDED15-IDED0 H L H L H L H L H L H L
tRP
tSR tRFS
IDE ultra DMA mode data-out end timing
IDEDRQ IDEDAKB IDEIOWB (STOP) IDEIORB (HDMARDY) IDEIORDY (DSTROBE) IDED15-IDED0 IDECS1B, IDECS0B IDEA2-IDEA0 H L H L H L tSS H L H L H L H L tACK tDVS tDVH
CRC
tLI tLI
tMLI
tACK tIORYZ
tLI
tACK
IDE ultra DMA mode data skew timing
t2CYC IDEIORB (Output side) H L tDVS H IDED15-IDED0 L (Output side) Delay, skew, etc., by cable IDEIORDY (Input side) IDED15-IDED0 (Input side) H L H L Output side Input side xSTROBE DD0 : : DD15
Data
tCYC tDVH
Data
tCYC
Data
tDS
tDH
Data Sheet S16302EJ3V0DS
35
PD720130
Serial ROM access timing
tHIGH tLOW SCL tSU.STA SDA (Output) tAA SDA (Input) tDH tBUF tHD.STA tHD.DAT tSU.DAT tSU.STO tLOW
Serial ROM write cycle timing
PIO1
PIO0 Word n
8th bit
ACK
tWR Stop condition Start condition
36
Data Sheet S16302EJ3V0DS
PD720130
4. PACKAGE DRAWING
* PD720130GC-9EU
100-PIN PLASTIC TQFP (FINE PITCH) (14x14)
A B
75 76 51 50
detail of lead end S C D P T
R
100 1 26 25
L U
F G H I
M
Q J K S N S M
NOTE Each lead centerline is located within 0.08 mm of its true position (T.P.) at maximum material condition.
ITEM A B C D F G H I J K L M N P Q R S T U
MILLIMETERS 16.00.2 14.00.2 14.00.2 16.00.2 1.0 1.0 0.220.05 0.08 0.5 (T.P.) 1.00.2 0.5 0.17 +0.03 -0.07 0.08 1.0 0.10.05 3 +4 -3 1.10.1 0.25 0.60.15 P100GC-50-9EU
Data Sheet S16302EJ3V0DS
37
PD720130
* PD720130GC-9EU-SIN
100-PIN PLASTIC TQFP (FINE PITCH) (14x14)
A B
75 76 51 50
detail of lead end S C D Q R
100 1
26 25
F G H P I
M
J
K
N
S
L M
NOTE Each lead centerline is located within 0.10 mm of its true position (T.P.) at maximum material condition.
ITEM A B C D F G H I J K L M N P Q R S
MILLIMETERS 16.00.2 14.00.2 14.00.2 16.00.2 1.0 1.0 0.22 +0.05 -0.04 0.10 0.5 (T.P.) 1.00.2 0.50.2 0.145+0.055 -0.045 0.10 1.00.1 0.10.05 3 +7 -3 1.27 MAX. S100GC-50-9EU-2
38
Data Sheet S16302EJ3V0DS
PD720130
5. RECOMMENDED SOLDERING CONDITIONS
The PD720130 should be soldered and mounted under the following recommended conditions. For soldering methods and conditions other than those recommended below, contact your NEC Electronics sales representative. For technical information, see the following website. Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index.html)
PD720130GC-9EU:
Soldering Method Infrared reflow
100-pin plastic TQFP (Fine pitch) (14 x 14)
Soldering Conditions Package peak temperature: 235C, Time: 30 seconds max. (at 210C or higher), Count: Two times or less Exposure limit: 3 daysNote (after that, prebake at 125C for 10 hours) Symbol IR35-103-2
Partial heating
Pin temperature: 300C max., Time: 3 seconds or less (per pin row)
-
Note After opening the dry pack, store it at 25C or less and 65% RH or less for the allowable storage period.
PD720130GC-9EU-SIN: 100-pin plastic TQFP (Fine pitch) (14 x 14)
Soldering Method Infrared reflow Soldering Conditions Package peak temperature: 235C, Time: 30 seconds max. (at 210C or higher), Count: Two times or less Exposure limit: 3 daysNote (after that, prebake at 125C for 10 hours) Partial heating Pin temperature: 300C max., Time: 3 seconds or less (per pin row) - Symbol IR35-103-2
Note After opening the dry pack, store it at 25C or less and 65% RH or less for the allowable storage period.
Data Sheet S16302EJ3V0DS
39
PD720130
[MEMO]
40
Data Sheet S16302EJ3V0DS
PD720130
[MEMO]
Data Sheet S16302EJ3V0DS
41
PD720130
[MEMO]
42
Data Sheet S16302EJ3V0DS
PD720130
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
Data Sheet S16302EJ3V0DS
43
PD720130
EEPROM is a trademark of NEC Electronics Corporation. USB logo is a trademark of USB Implementers Forum, Inc.
* The information in this document is current as of June, 2003. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may appear in this document. * NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others. * Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. * While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC Electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. * NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to NEC Electronics products developed based on a customerdesignated "quality assurance program" for a specific application. The recommended applications of an NEC Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of each NEC Electronics product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to determine NEC Electronics' willingness to support a given application. (Note) (1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its majority-owned subsidiaries. (2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as defined above).
M8E 02. 11-1

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